Senior DFT Engineer

Your Responsibilities Will Include:

·    Partitioning for ATPG and hierarchical approaches

·    ATPG compression and serialization

·    RTL-Scan insertion and design rule fixing

·    Expertise in Memory BIST including Memory Repair, In-System Test (IST) for Memories from Implementation to Verification and Silicon Debug

·    Experience on Boundary Scan and writing DFT mode constraints for IP's and providing the timing feedback to STA team for DFT modes

·    Experience on DFT RTL generation and Integration with RTL level QC checks like Spyglass LINT, Spyglass DFT and Fishtail

·    Familiar with IEEE1149.1, IEEE1500 and IEEE1687 standards

·    Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations

·    Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis

·    Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE

·    Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE

·    Having experience with state-of-the-art, industry-standard DFT tools

·    Being hands-on from the nitty-gritty details to high-level planning

Minimum Qualifications:

·    BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field

·    7+ years of experience with DFT technologies, including scan test and MBIST

·    Experience with a hardware description language such as Verilog, System Verilog, or VHDL

·   Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.)

·    Ability to work well in a diverse team environment

·    Experience delivering detailed technical documentation