Scripting, Python, Routing, Tcl, CTS, primetime, 3D IC, ICC2, Cadence, LVS, IR Drop, Calibre, Innovus, Physical Verification, HBM, Placement, Si, Chiplets, floorplanning, EM, Full-Chip Physical Design, Advanced Packaging, Timing Closure, DRC, Advanced nodes 7nm or below, 2.5D, EDA Tools, Synopsys

power integrity , primetime, full-chip integration, physical verification tools, Timing Closure, Cadence Innovus, Synopsys ICC2, signoff flows

redhawk , Python Scripting, Tcl Scripting, Innovus ICC2, primetime, StarRC, Formality, ICC2 Fusion Compiler, Voltus

Verilog, Computer Architecture, Subsystem hardening, Synthesis, object-oriented programming, floorplanning, Place And Route, DFT insertion, digital logic, VHDL, RTL-to-GDSII implementation, EDA Tools, Timing Closure, Clock Tree Synthesis

Tcl, Verilog, Python, Perl, Computer Architecture, VHDL, object-oriented programming, Subsystem hardening, EDA Tools, Place And Route, digital logic, DFT insertion, floorplanning, RTL-to-GDSII implementation, Synthesis, Timing Closure, Clock Tree Synthesis