Physical Design Manager

Job Title: Physical Design SoC Lead / Manager (Full Chip)

Job Description:

Lead full-chip physical design implementation for advanced SoCs from netlist to tapeout. Own floorplanning, power planning, placement, CTS, routing, timing closure, IR/EM analysis, and physical signoff. Drive PPA optimization and ensure design quality, schedule, and tapeout readiness. Collaborate with RTL, STA, DFT, package, CAD, and foundry teams to resolve technical challenges and achieve project milestones. Mentor and lead physical design engineers, define implementation methodologies, and provide technical leadership across multiple tapeout programs.

Requirements:

• 10+ years of physical design experience with multiple successful SoC tapeouts.
• Strong expertise in full-chip integration, timing closure, power integrity, and signoff flows.
• Proficiency with Cadence Innovus, Synopsys ICC2, PrimeTime, and physical verification tools.
• Experience at advanced technology nodes (16nm and below preferred).
• Proven technical leadership and team management skills.