Jtag, Perl, Verilog, Python, Tcl, Sta, MBIST, Siemens Tessent, Synopsys TestMAX, systemverilog, DFT Compiler, Scan Insertion, Physical Design, Cadence Modus, RTL synthesis, ATPG, Scan Compression, DFT Architecture

power integrity , Routing, Perl, Python, Tcl, Chip finishing, Metal fill, Clock Trees, Tapeout checks, Physical Verification, Sealring, Signal Integrity, RTL2GDS flow, Floorplans, Power Distribution Network, Physical Design, Timing Closure, Placement, Physical Sign off, Equivalence Check, Synthesis Constraints

C, Gdb, Eclipse, Gcc, Gnu Make, JIRA, Git, Confluence, Python, DC to AC inverters, Zephyr RTOS, AC grid simulators, Atlassian cloud suite, Closed-loop control algorithms, ARM Cortex-M4

Ml, Automation, Database Architecture, Project Management, Ai, monte, Spice

Ipsec, Wireshark, Gcp, Terraform, Tcpdump, BGP, Azure, Python, AWS, Go, Gre

Scripting, Java, C, Computer Architecture, Linux Internals, Python, Operating System Concepts, Device Drivers, Assembly