simvision , Shell, Vcs, Python, Tcl, Verdi, Xcelium, QuestaSim, Uvm, systemverilog

DDR, Pcie, Ethernet, SRIO, RDMA, verification of ARM RISC-V based sub-systems or SoCs, IP or integration verification of high-speed interfaces, Design Verification, ROCE, RDMA TSO, automated flows and scripts for data exploration analysis and performance verification, 400G Mac, LRO, Congestion Control, waveform debugging tools, PSP, Simulators, SV Assertions, HBM, Formal Emulation, UVM based verification environments, RDMA over converged Ethernet

cache coherency , Soc Architecture, DDR, Shell, Perl, Pcie, Ethernet, Python, Tcl, memory subsystems, Cadence Xcelium, checkers, Uvm, UCIe, coverage-driven verification, Assertions, systemverilog, Synopsys VCS, protocol compliance scoreboards, VIP integration, interrupts, SVA

Regression Testing, Debugging, Functional Coverage, Axi, APB, AMBA Protocols, Uvm, AHB, Assertions, systemverilog, SVA

ASICs, formal verification, GLS low-power DV, LPDDR, Uvm, assertion-based verification, memory system architecture, systemverilog, standard IP components, performance verification

Jtag, Perl, Verilog, Shell scripting, Python, Tcl, Functional Coverage, Assertions SVA, Cadence Xcelium, MBIST, Uvm, systemverilog, Siemens Questa, Synopsys VCS, Dft, ATPG, DFX, Scan, LBIST

Python, Tcl, Analog mixed-signal IC design, Verilog-AMS, AMS Designer, behavioral modeling, Cadence Virtuoso, Verification, systemverilog, Spectre

C, Python, low-power verification techniques, Design Verification, Uvm, systemverilog, co-simulation, SoC-level verification, formal verification methodologies, AI-assisted development tools, EDA Tools, ABV, HDL verification languages, SVA

Verilog, Scripting Languages, Verification Tools, Simulators, formal verification, VHDL, Uvm