Lead Design Verification Engineer

Lead Design Verification Engineer

Location: Bengaluru

Experience: 5–10 Years

Role Overview

We are seeking a highly skilled Lead Design Verification Engineer to drive verification of complex IPs and SoCs. The role requires deep expertise in SystemVerilog, UVM, and high-speed protocols with strong ownership of verification architecture, coverage closure, and debug.

Key Responsibilities

• Develop and execute verification strategies for complex SoC and IP designs.
• Build scalable UVM-based testbenches, verification environments, and reusable VIPs.
• Define verification plans, functional coverage models, assertions, and regression methodologies.
• Drive end-to-end verification closure, debug, and performance analysis.
• Collaborate closely with RTL, Architecture, Firmware, and Post-Silicon teams.
• Mentor junior engineers and drive verification methodology improvements.

Technical Skills

• Strong expertise in SystemVerilog, UVM, Assertions (SVA), and coverage-driven verification.
• Hands-on experience verifying high-speed protocols such as PCIe, UCIe, Ethernet, DDR, and related subsystems.
• Experience with protocol compliance, scoreboards, checkers, and VIP integration.
• Good understanding of SoC architecture, cache coherency, interrupts, and memory subsystems.
• Proficiency in scripting using Python, Perl, Shell, or Tcl.
• Experience with Synopsys VCS, Cadence Xcelium, or equivalent simulation tools.
• Exposure to emulation, formal verification, and low-power verification is a plus.

Qualifications

• B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, Computer Engineering, or related fields.
• Proven track record of delivering first-pass silicon through robust verification methodologies.