Pcie, Version Control, Ethernet, RTL synthesis, Documentation, Timing Closure, verification processes, silicon bring-up, bare metal firmware development, SERDES, AI tools like Cursor

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

Physical Design, Timing Closure, Power Planning, Deep sub-micron technology issues, Floor Planning, Signal integrity analysis, Place And Route

Routing Protocols, network management, DWDM, Vlans, IP networking concepts, ROADM, Ethernet over Optical, Infinera platforms

Ovm, DDR, Pcie, Python, Tso, Perl, Ethernet, Arm, Tcl, systemverilog, RISC-V, LRO, Uvm, AI Compute, SV Assertions, HBM, Formal Emulation, Die-to-Die Interconnects, RDMA, High-Speed IO Interconnects, RoCE, NIC, 400G MAC, TimeSync protocols, revision control systems

Verilog, Design Verification, implement IP/SoC verification plans, systemverilog, C/C++, ASIC development cycles