Hard IP integration, Clock and Power distribution, STA setup convergence methodology, Power Integrity Analysis, Hierarchical design implementation, Automation scripts within STA tools, Timing Closure, Timing ECO Implementation strategy, Floor Planning, Debugging skills in implementation issues, ASIC Physical implementation, Global signal planning, Physical convergence, Tweaker Primetime based ECO flows

Perl, Python, Tcl, Emulation, systemverilog, System Verilog Assertions

Uart, Spi, Pcie, Verilog, I2c, Unix Systems, Otn, Uvm, Microsemi FPGAs, systemverilog, Ethernet-based protocols, quartus, VHDL, scripting tools, Vivado, VMM, AXI memory controllers, Libero

power optimization , C, Unix Shell, Linux, Perl, Tcl, Advanced STA concepts, Physical Design Flow, Block level PnR convergence, Cadence Innovus, LVS, Timing convergence, PTSI Tempus, Physical Verification, Timing Closure, DRC, PDN, Floor-planning, Place And Route, Synopsys ICC2, formal verification

power integrity , Routing, Perl, Python, Tcl, Chip finishing, Metal fill, Clock Trees, Tapeout checks, Physical Verification, Sealring, Signal Integrity, RTL2GDS flow, Floorplans, Power Distribution Network, Physical Design, Timing Closure, Placement, Physical Sign off, Equivalence Check, Synthesis Constraints

simvision , Shell, Vcs, Python, Tcl, Verdi, Xcelium, QuestaSim, Uvm, systemverilog

simvision , pipelining , Vcs, Verilog, Static Timing Analysis, Design Compiler, primetime, Xcelium, clock domain crossing, Waveform tools, VHDL, Genus, RTL design and simulation tools, Digital logic design concepts, Verdi, Synthesis tools, systemverilog, Axi, FPGA ASIC design flow, BUS Protocols, Fsms, APB, Modelsim, AHB, Low-power design techniques