
Search by job, company or skills
Responsibilities:
Required Skills and Experience:
Job ID: 151001481
Skills:
FPGA Design, Static Timing Analysis, Synthesis, Timing Closure, systemverilog, Code coverage analysis, RTL design using Verilog
Skills:
memory controllers , Uart, Spi, Hdl Languages, Pcie, Verilog, I2c, Unix Systems, Otn, Uvm, Microsemi FPGAs, systemverilog, Ethernet-based protocols, Axi, quartus, VHDL, scripting tools, Vivado, VMM, Libero
Skills:
FPGA Design, Verilog, systemverilog, Xilinx Vivado, altera quartus, Peripheral Protocols
Skills:
hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, test benches, Rtl Design, UVM verification flow, Synthesis, Timing Closure, Verification, Debug, Simulation
Skills:
Fast Fourier Transform, Digital Signal Processing, Verilog, System Verilog, Xilinx FPGA architectures, FPGA development, OFDM, complex algebra, Vivado, Rtl Design, linear algebra, AXI4 Lite, AXI4 Stream, baseband processing
We don’t charge any money for job offers