Jtag, Perl, Verilog, Shell scripting, Python, Tcl, Functional Coverage, Assertions SVA, Cadence Xcelium, MBIST, Uvm, systemverilog, Siemens Questa, Synopsys VCS, Dft, ATPG, DFX, Scan, LBIST

Shell, Perl, Python, PCIe Gen4, Verification Methodologies, CXL 1.x, Uvm, Assertions, systemverilog, SVA, Coverage-Driven Verification

Ovm, System Verilog, Uvm, constrained random verification methodologies, FPGA prototyping, FPGA architecture, Pre Silicon Validation Verification

Tcl Scripting, Pcie, Perl, System Verilog, Python, verification methodologies, CHI, performance power optimization, SMMU, assertion-based verification, Uvm, UPF, Coresight, Axi, formal verification, power-aware verification, coverage-driven testing, CXL, SVA

Jenkins, Verilog, Makefile, Python, Functional Coverage, Uvm, systemverilog

Regression Analysis, Cadence Xcelium, Top-Level Verification, wreal Modeling, model validation, Cadence VIVA, Schematic-Level Correlation, Uvm, Coverage-Driven Verification, Analog Circuit Fundamentals, Waveform Debug, SV-RNM, Verification Planning, Cadence ADE Assembler, Simulation Debug, SoC AMS Verification, Digital Design Flow, Mixed-Signal SoC Integration, systemverilog, Verilog-AMS, Cadence SimVision, Cadence Virtuoso, AMS Verification Methodology, Mixed-Signal Verification