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fiveforce technologies

Lead Engineer - Design Verification

fiveforce technologies
Bengaluru, India
10-12 Years
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  • Posted 9 days ago
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Job Description

About The Opportunity

A fast-scaling engineering services firm in the Semiconductor & Electronics Design Verification sector, we partner with global chipmakers to validate complex SoC, IP, and RTL designs at scale. Our team builds next-gen verification environments using cutting-edge methodologies and automation to deliver silicon with zero escapes—helping clients de-risk tapeouts and accelerate time-to-market.

Role & Responsibilities

  • Should have atleast 10 Years of relevant experience in DV and have handled a team size of atleast 10 members.
  • Lead end-to-end design verification for complex digital IPs and SoCs—from testbench architecture to coverage closure and regression management.
  • Architect and implement scalable UVM-based verification environments with constrained-random stimulus, functional coverage, and scoreboard logic.
  • Define and enforce verification sign-off criteria, including code coverage, functional coverage, and assertion coverage metrics across multiple design blocks.
  • Mentor junior engineers on UVM best practices, debug methodologies, and verification productivity tools; drive team-wide adoption of reusable verification IP (VIP).
  • Collaborate with design and DFT teams to align verification strategy with testability, clock domains, and power intent; ensure coverage of corner cases and failure modes.
  • Automate regression flows using Python/Makefiles/Shell scripts; integrate CI/CD pipelines with Jenkins or equivalent tooling for nightly regression and gating checks.

Skills & Qualifications

Must-Have

  • UVM
  • SystemVerilog
  • Verilog
  • Functional Coverage
  • SV Assertions (SVA)
  • Makefile
  • Python
  • Jenkins

Preferred

  • Formal Verification ( JasperGold / Questa Formal )
  • Verification IP (VIP) development
  • EDA Tools (VCS, Xcelium, Questa)

Benefits & Culture Highlights

  • Comprehensive Health & Wellness: Full medical, dental, and vision insurance coverage; mental health support via telehealth platforms; wellness stipends and annual health check-ups.
  • Financial Security: Competitive salary with performance-based bonuses; 401(k)/retirement savings plan with company match; life and disability insurance.
  • Work-Life Balance: Generous paid time off (PTO) — 20+ days annually, plus paid holidays and sick leave; flexible hybrid/remote work model post onboarding.
  • Professional Growth: Technical career ladder with merit-based promotions; quarterly upskilling sprints (e.g., UVM Advanced, Formal, AI for Verification); annual learning stipend for certifications and conferences.
  • State-of-the-Art Resources: Access to cutting-edge EDA tools (e.g., Synopsys, Cadence, Siemens EDA), cloud-based verification farms, and high-performance computing environments.
  • Inclusive & Innovative Culture: Collaborative, diverse teams; employee resource groups; innovation incubators for verification automation and AI-driven verification experiments.

Skills: systemverilog,verilog,uvm,

More Info

Job Type:
Permanent Job
Industry:
Other
Function:
Semiconductor Electronics Design Verification
Employment Type:
Full time

Job ID: 150512159

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Last Updated: 30-06-2026 07:59:03 PM
Homejobs in Bengaluru / BangaloreLead Engineer - Design Verification

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