Pcie, Ovm, Axi, AMBA, CHI, Ace, interconnect and bus protocols, cache coherency concepts, CXL, Uvm, systemverilog

Verilog, Scripting Languages, Verification Tools, Simulators, formal verification, VHDL, Uvm

Analog and mixed signal electronic parts, Software simulations, Design Verification, Integrated circuitry

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, congestion control, regression systems, systemverilog, vector processing units, full verification life cycle, revision control systems, AI ML Accelerators, constrained-random verification environments, packet processing, Verification

Vcs, Shell, Perl, Python, PCIe Gen5, Xcelium, Uvm, systemverilog, AMBA, Axi, APB, Questa, CXL, AHB, SVA

Debugging, Automated Test Scripts, Documentation, Design Verification, Functional Verification, Test Plan Development

analog circuits , Fpga, Logic Design, Verilog, Micro-architecture, Synthesis, Uvm, Timing Constraints, Regression frameworks, Power product design, System-Verilog, Functional Verification, RTL Coding, Sta, Synthesis scripts, ATPG generation, Scan Insertion, formal verification, ABV, Timing Analysis, Digital Verification

Spi, I2c, Uart, Pcie, Usb, Noc, cdc, SoC IP Design, AMBA protocols, Network on Chip

Spi, I2c, Gpio, Uart, Pcie, DDR, UVM methodology, I3C, QSPI, CXL, systemverilog, HBM

Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping