Senior Design Verification Engineer

Senior Design Verification Engineer

Location: Bengaluru, India

Experience: 5+ Years

Role:

Drive end-to-end verification of next-generation PCIe Gen5/Gen6/Gen7 IPs and SoCs by building scalable UVM environments, developing robust verification strategies, and ensuring first-pass silicon success.

Responsibilities

• Verify PCIe Gen5/6/7 Controller and Subsystem IPs using SystemVerilog/UVM.
• Develop reusable UVM testbenches, assertions, scoreboards, coverage models, and constrained-random testcases.
• Perform protocol compliance, functional verification, regression, and coverage closure.
• Debug RTL and verification issues in collaboration with design and architecture teams.
• Contribute to verification methodology and mentor junior engineers.

Requirements

• 5+ years of ASIC/SoC Design Verification experience.
• Strong expertise in SystemVerilog, UVM, and SVA.
• Deep understanding of PCIe Gen5/Gen6/Gen7 protocol.
• Experience with VCS, Xcelium, or Questa, functional coverage, and protocol debugging.
• Scripting skills in Python/Perl/Shell.
• Exposure to CXL or AMBA (AXI/AHB/APB) is a plus.

Preferred Qualification: Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.