simvision , Shell, Vcs, Python, Tcl, Verdi, Xcelium, QuestaSim, Uvm, systemverilog

DDR, Pcie, Ethernet, SRIO, RDMA, verification of ARM RISC-V based sub-systems or SoCs, IP or integration verification of high-speed interfaces, Design Verification, ROCE, RDMA TSO, automated flows and scripts for data exploration analysis and performance verification, 400G Mac, LRO, Congestion Control, waveform debugging tools, PSP, Simulators, SV Assertions, HBM, Formal Emulation, UVM based verification environments, RDMA over converged Ethernet

cache coherency , Soc Architecture, DDR, Shell, Perl, Pcie, Ethernet, Python, Tcl, memory subsystems, Cadence Xcelium, checkers, Uvm, UCIe, coverage-driven verification, Assertions, systemverilog, Synopsys VCS, protocol compliance scoreboards, VIP integration, interrupts, SVA

C, Python, low-power verification techniques, Design Verification, Uvm, systemverilog, co-simulation, SoC-level verification, formal verification methodologies, AI-assisted development tools, EDA Tools, ABV, HDL verification languages, SVA

Ovm, System Verilog, Uvm, constrained random verification methodologies, FPGA prototyping, FPGA architecture, Pre Silicon Validation Verification

Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

ASICs, formal verification, GLS low-power DV, LPDDR, Uvm, assertion-based verification, memory system architecture, systemverilog, standard IP components, performance verification