DDR, Pcie, Verilog, Ethernet, Python, Cadence Incisive, UCIe, Uvm, Synopsys VCS, formal verification, VHDL, Modelsim

performance verification of ASICs, ASIC standard interfaces, verification components, formal tools, Design Verification, assertion-based verification, Uvm, systemverilog, memory system architecture

DDR, Pcie, Ethernet, SRIO, RDMA, verification of ARM RISC-V based sub-systems or SoCs, IP or integration verification of high-speed interfaces, Design Verification, ROCE, RDMA TSO, automated flows and scripts for data exploration analysis and performance verification, 400G Mac, LRO, Congestion Control, waveform debugging tools, PSP, Simulators, SV Assertions, HBM, Formal Emulation, UVM based verification environments, RDMA over converged Ethernet

cache coherency , Soc Architecture, DDR, Shell, Perl, Pcie, Ethernet, Python, Tcl, memory subsystems, Cadence Xcelium, checkers, Uvm, UCIe, coverage-driven verification, Assertions, systemverilog, Synopsys VCS, protocol compliance scoreboards, VIP integration, interrupts, SVA

C, Python, low-power verification techniques, Design Verification, Uvm, systemverilog, co-simulation, SoC-level verification, formal verification methodologies, AI-assisted development tools, EDA Tools, ABV, HDL verification languages, SVA

Ovm, System Verilog, Uvm, constrained random verification methodologies, FPGA prototyping, FPGA architecture, Pre Silicon Validation Verification

Analog and mixed signal electronic parts, Software simulations, Design Verification, Integrated circuitry

Regression Testing, Debugging, Functional Coverage, Axi, APB, AMBA Protocols, Uvm, AHB, Assertions, systemverilog, SVA

simvision , Shell, Vcs, Python, Tcl, Verdi, Xcelium, QuestaSim, Uvm, systemverilog