FinFET technologies, physical implementation, Analog Layout, Analog Mixed Signal Layout, advanced node designs

Analog and Analog Circuits fundamentals, Circuit Design concepts, Layout Design for standard cells, CMOS process design rules

Analog Mixed-Signal Layout, MOS resistor capacitor current mirror differential pair and analog IP layouts, DRC LVS ERC and PEX, advanced matching and layout techniques, Cadence Virtuoso Custom Compiler, FinFET advanced-node layout, lower-node technologies

Schematic layout tools, Technical reports and communications, Design FMEA creation and revisions, Analog and digital design, Test plans and test reports

Routing, Pvs, PERL, Tcl, R3D, PEX, LVS, Layout Techniques, Verification, Skill Programming, CAD Tools, Calibre, Analog Layout, ERC, VCAR, DRC, VSR, virtuoso

analog layout techniques, Mentor tools, reliability requirements, LVS, layout tools, Calibre, EMIR, ERC, Optimization, Esd, DRC, Parasitic Extraction, Antenna, Cadence Virtuoso, flat layout methodologies