Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

Perl, Python, Formal Verification methodologies, Axi, APB, JasperGold, AMBA protocols, VC Formal, Uvm, AHB, systemverilog

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Usb, C, Uart, Bash, Spi, Pcie, Perl, Verilog, I2c, Test Plan Creation, Python, System Verilog, Tcl, gate-level simulations, verification methodology, i2s, Uvm, DP, Sd, Test Development, test-bench development, Gate Level Power-Aware simulations, test coverage assessment

Azure - AKS, Python, Sql, Github, Docker, Arm

Software Release Management, Shell scripting, Deployment Git, WLAN standards IEEE 802.11, Automation using Python

monte carlo , python, AI ML, Cadence Virtuoso, Spice Simulator