Senior Staff Engineer – Design Verification
Location: Bengaluru
Experience: 10–15 Years
Role Overview:
We are looking for a Senior Staff Engineer – Design Verification with 10+ years of experience and deep expertise in testbench architecture and IP-level verification. The role will own the verification strategy and on-time, high-quality delivery of complex digital IPs, while driving technical execution across the verification lifecycle.
Key Responsibilities
- Own verification architecture, strategy, planning, execution, and quality for complex digital IPs.
- Architect and develop scalable SystemVerilog/UVM testbenches for IP-level verification.
- Define and review verification plans (VPlan), test strategies, coverage goals, and regression methodology.
- Drive functional, performance, stress, corner-case, and negative testing.
- Own coverage closure, including functional and code coverage, and identify verification gaps.
- Develop reusable UVM agents, sequences, scoreboards, monitors, reference models, and checkers.
- Lead regression execution, debug, failure triage, and root-cause analysis.
- Verify complex designs involving AMBA AXI, AHB, and APB protocols.
- Drive performance verification, including throughput, latency, bandwidth, backpressure, and stress scenarios.
- Leverage formal verification to complement simulation-based verification and improve verification quality.
- Collaborate closely with RTL Design, Architecture, Performance, DFT, and SoC teams to resolve functional and system-level issues.
- Mentor senior/junior verification engineers and drive verification methodology improvements.
- Ensure predictable execution against quality, coverage, schedule, and tape-out milestones.
Required Technical Expertise
- 10+ years of hands-on experience in Design Verification.
- Deep expertise in SystemVerilog and UVM.
- Strong experience architecting IP-level verification environments for complex digital IPs.
- Proven ownership of VPlan, testbench architecture, regressions, coverage analysis, and coverage closure.
- Strong understanding of AMBA protocols – AXI, AHB, and APB.
- Strong experience in performance verification and performance bottleneck analysis.
- Hands-on experience with Synopsys VCS and/or Cadence simulation tools.
- Working experience with JasperGold and/or Synopsys VC Formal.
- Strong debugging skills across RTL, simulation, assertions, protocol, and performance issues.
- Strong scripting/programming skills in Python, Perl, Tcl, or equivalent.
Preferred Qualifications
- Experience verifying high-performance or complex SoC/IP subsystems.
- Strong knowledge of SVA, constrained-random verification, assertions, scoreboarding, reference models, and functional coverage.
- Experience integrating formal and simulation-based verification flows.
- Proven track record of technical leadership and end-to-end verification ownership.
- Strong communication and cross-functional leadership skills.
