Fpga, Logic Design, Verilog, Uvm, Timing Constraints, TCL scripts, regression frameworks, Timing Analysis, Power product design, System-Verilog, RTL Coding, Functional Verification, Sta, micro-architecture, ATPG generation, formal verification, synthesis scripts, Synthesis, ABV, design constraints, Digital Verification, Scan Insertion

Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog

Asic verification, digital design verification, Uvm, test bench architecture, systemverilog, GIT version control, C Language