Design Verification Engineer
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Experience: 4-5 Years
Location: Bangalore/Hyderabad
Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics
Roles and Responsibilities
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Job ID: 152434311
Skills:
wireless protocols , modem, System Verilog, Wifi Standards, constraint random tests, assertion coverage-based verification methodology, debugging RTL TB issues using Verdi, Uvm, formal static verification methodologies
Skills:
DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm
Skills:
C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency
Skills:
Verilog, systemverilog, assertion-based verification, Uvm, functional coverage, advanced verification methodologies, VMM, random stimulus
Skills:
Fpga, Usb, Python, Pcie, Perl, Emulation, directed constrained-random tests, Uvm, AXI4, coverage driven verification, Test Bench, verification methodologies, systemverilog, transaction level modeling, AMBA, MIPI, formal verification
