Lead Design Verification Engineer
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Lead Design Verification Engineer
Location: Bengaluru, India
Experience: 7–12 Years
Role
Lead the verification of complex IPs and SoCs, driving end-to-end verification strategy, methodology, and signoff for high-performance silicon.
What You'll Do
What You Bring
Preferred
We're looking for engineers who build robust verification infrastructure, solve complex silicon challenges, and deliver first-pass silicon success through technical excellence.
Job ID: 152086153
Skills:
DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm
Skills:
Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, SystemVerilog UVM, Axi, CXL, SVA
Skills:
Soc Architecture, System Verilog, digital design concepts, UVM Universal Verification Methodology, debugging using waveforms and logs
Skills:
System Verilog, Axi, dv methodologies and tools, ACE-Lite, Bus protocols like AHB, Ace, Digital design concepts, LPDDR5 protocols, Debug, Uvm
Skills:
Doors, Tcl Scripting, FPGA Synthesis Place and Route, DO-254 development process, RTL development using VHDL, Hardware system design knowledge of digital logic, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, FPGA design tools like Libero, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory
