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Memory Layout Design Engineer

  • Posted 8 days ago
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Job Description

Job Description:

Job Requirements:

  • Minimum 3 years of experience with strong layout knowledge.
  • Bachelor's degree required.
  • Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - CALIBRE & Hercules).
  • Strong layout knowledge in submicron processes (e.g., A14, 2nm, 3nm, 5nm, 7nm).
  • Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.

Job Description:

  • Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
  • Manage scheduling, timelines, and layout floor-planning.
  • Responsible for start-to-end deliverables with quality within the planned schedule.
  • Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.

Skill Set (Memory):

  • Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.
  • Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.
  • Proficiency in floor-planning, hierarchy layout, and chip integration.
  • Understanding of memory architecture, RC requirements, and the ability to plan signal and power based on layout guidelines.
  • Knowledge of AI, automation in layout, Script Programming, and SKILL Programming is a plus.
  • Ability to lead, train junior engineers, and manage projects effectively.
  • Good knowledge of memory layout topology; experience with memory compilers is a plus.
  • Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
  • Self-reliant with the ability to work both independently and collaboratively.

R026842


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Job ID: 152914519

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