JOB DESCRIPTION
Position: Sr DFT Engineer (Lead)– ATPG & Scan Insertion
Experience: 12–15 Years
Role Overview
We are looking for a Senior DFT Engineer with deep expertise in ATPG and Scan Insertion to support high‑complexity SoC programs for our semiconductor clients. This role requires strong technical ownership across the DFT lifecycle and the ability to deliver manufacturing‑ready, high‑quality test solutions in a fast‑paced, multi‑stakeholder environment.
Key Responsibilities
- Lead DFT definition, implementation, and signoff for complex SoCs and IPs
- Own Scan Insertion and Scan Compression strategies aligned with performance, area, and test cost goals
- Develop, debug, and optimize ATPG patterns (stuck‑at, transition, at‑speed) to achieve high fault coverage
- Partner with client engineering teams across RTL, Synthesis, Physical Design, and Validation
- Identify and resolve DFT/ATPG bottlenecks, including coverage gaps and pattern inefficiencies
- Support silicon bring‑up, tester correlation, and customer test readiness milestones
- Ensure adherence to client DFT standards, schedules, and quality expectations
- Provide technical guidance and mentoring to junior DFT engineers on the project
Required Expertise
- 10–12 years of hands‑on experience in DFT implementation and ATPG signoff
- Strong working knowledge of:
- Scan architectures and scan compression methodologies
- Fault models: stuck‑at, transition, path delay
- At‑speed and timing‑aware ATPG
- Practical experience using leading commercial DFT tools (Synopsys, Cadence, or Siemens platforms)
- Strong understanding of RTL design flow, synthesis constraints, and timing concepts
- Proven ability to work with large, multi‑site client teams and meet aggressive program milestones
