UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog

Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB

python, Perl, System Verilog, DDR-IO verification, LPDDR JDEC specifications, Uvm, coverage driven verification methodology, LPDDR5

Spi, Uart, I2c, Ethernet, Can, DV firmware verification, GLS, Uvm, Specman, systemverilog, AMS CDC digital verification, post-silicon verification, AHB, C-based SoC design verification, UPF based verification, CSI, CPF, cybersecurity processes, AI ML based DV, formal verification, APB, Axi, functional safety, PAGLS

Ovm, DDR, Pcie, Python, Tso, Perl, Ethernet, Arm, Tcl, systemverilog, RISC-V, LRO, Uvm, AI Compute, SV Assertions, HBM, Formal Emulation, Die-to-Die Interconnects, RDMA, High-Speed IO Interconnects, RoCE, NIC, 400G MAC, TimeSync protocols, revision control systems

code coverage , Design Verification Engineer, Low Power Verification Engineer, Power-Aware Verification Engineer, ASIC Design Verification Engineer, systemverilog, Uvm, Constrained Random Verification, Gate-Level Simulation, Timing Simulation, PAGLS, Testbench Development, VIP Integration, Coverage Closure

SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification