System Integration, Matlab, IC System Partitioning, Routing Tradeoffs, Physical Layout Management, Signal Grounding, Block-level Modeling, Architectural Tradeoff Analysis, AMs, Spectre, Worst-case Identification, Monte Carlo Analysis, Device Physics Knowledge, Simplis, Post-layout Parasitic Extraction, Block-level Topology Selection, Top-level Verification, Schematic Generation

Schematic Design, Control-Loop Stability, power management, Analog Layout Effects, ESD Latch-Up, Mixed-Signal IC Development, Protection Circuits, Switching Converters, Extraction, Post-Layout Verification, Analog Design, References, Sensors, Data Converters, Charge Pumps, Signal-Conditioning Blocks, Simulation, IC-Level Robustness, LDOs, Analog Feedback Loops

Perl, Verilog, Python, scripting and automation tools, ISO26262, Formal verification methodologies, ADCs, Cadence, Automotive qualification, Uvm, systemverilog, Analog Circuit Design, DACs, Comparators, Op-Amps