Jtag, Perl, Verilog, Python, Tcl, Sta, MBIST, Siemens Tessent, Synopsys TestMAX, systemverilog, DFT Compiler, Scan Insertion, Physical Design, Cadence Modus, RTL synthesis, ATPG, Scan Compression, DFT Architecture

boundary scan , C, Perl, Verilog, System Verilog, Python, Tcl, Memory BIST, IEEE1687, Fishtail, IEEE1500, DFT RTL generation, IEEE1149.1, ATPG SAF, Spyglass DFT, VHDL, MBIST verification, ATPG, TDF, Spyglass LINT

DFT verification, IEEE1149, CTL generation, MBIST, Scan, ASIC SoC designs, DFT validation, 1500, 1687, DFT EDA tools, Dft, timing generating test cases, Analog IPs, HSIOs, debugging GLS

Perl, Tcl, Skill, EDA Tools, Cadence Virtuoso

PERL, Python, Tcl, Sta, RTL-GDS flows, Physical Verification, SNPS CAD Flow, SNPS CDNS-based tools

Unix, Perl, Linux, Shell scripting, Python, Tcl, Place Route Cadence Innovus, Physical Verification Calibre DRC LVS, IR EM Cadence Voltus RedHawk, STA Cadence Tempus

Tcl Scripting, Python, Synopsys DFT flow, Tool installation configuration, Dft, PrimePower, Virtuoso SI2 scripting, virtuoso, LEC, Voltus RedHawk, Power and signoff flow automation

boundary scan , Technical Leadership, Perl, Python, Tcl, test compression, scan compression, DFT signoff, test access strategies, pattern optimization, DFT methodologies, MBIST, DFT architecture definition, Failure Analysis, ATPG, silicon bring-up, yield ramp, LBIST