C, Spi, Verilog, I2c, Python, C++, Uart, Perl, Real Number Modeling, LNA, Analog IC design, LVS, Bias bandgap, VHDL, Cadence IC design tools, Filters, LDO, Layout experience using Cadence flow, VerilogAMS, Charge pump, Opamp, systemverilog, MIPI, DRC, VerilogA

Matlab, Worst case identification, Monte Carlo analysis, Block level topology selection, AMs, Analog Circuit Design, Spectre, Cadence tool set, Top level simulation, Simplis, IC system partitioning and architectural tradeoff analysis, Hand analysis and IC transistor level implementation, Post layout parasitic extraction, Schematic generation and simulation on modern CAD tools

references, analog mixed-signal IC design, ADCs, Cadence, mixed-signal design, PGAs, Spectre, DACs, Calibre, interfacing with microcontrollers, low-noise amplifiers, virtuoso, on-chip power blocks

Modeling, automation techniques, reusable intellectual property, circuit design verification, silicon correlation, analog and mixed-signal IC design, semiconductor device physics, CMOS technologies, AI-driven engineering tools, product qualification, DRAM, advanced process nodes

bandgap references , temperature sensors , frequency response, Sigma-Delta converters, mismatch analysis, op-amps, AMs, precision analog circuits, ip development, AC simulations, Layout XL, ADEXL, Cadence Virtuoso suite, Schematic Maestro, mixed-signal circuit design, DC operating point, biasing circuits, noise, INL, Spectre, DNL, Stability, CMOS technologies, LDOs, THD

Cadence Virtuoso, High-Speed ADC Design, EDA Tools, Post-silicon validation, Analog IC Design, Mixed-Signal IC Design

CMOS BCD Analog Circuits, power management, Design Reviews, Mass production test plan, Quality assurance test plan