Silicon Validation, Analog Circuit Design, Monte Carlo analysis, Modern CAD tools, Design extraction, Debug, Simulation and Verification, Simulation flows, Block designs, Schematic generation

Matlab, Worst case identification, Process technologies, Monte Carlo analysis, Simulation verification, Block level topology selection, IC system partitioning, Physical layout management, AMs, Simulation on modern CAD tools, Analog Circuit Design, Architectural tradeoff analysis, Schematic generation, Routing tradeoffs, Spectre, Cadence tool set, Signal grounding, Top level simulation, Simplis, device physics, Post layout parasitic extraction, Die area optimization

UNIX, signals systems and transforms, AC DC analysis, circuit simulation tools, MOS transistors, High Volume Manufacturing, feedback systems, end-to-end design flow, poles zeros compensation, layout tradeoffs, Analog Circuit Design, Mixed Signal Design, Modeling Tools, layout verification tools, CMOS Bi-CMOS fabrication processes, loop dynamics, device physics

chip top-level ownership, Virtuoso Cadence, reliability simulations, silicon debug expertise, Analog Circuit Design

regulators , Verilog, Matlab, RX, deep sub-micron CMOS technologies, TX, IC design CAD tools, Mixed signal circuits, high-speed design techniques, Spectre, PLLs, DACs, Spice, Filters, ADCs, HSIM, Bandgap bias circuits

Full product development cycle, Quality requirements for automotive products, power management, CMOS BCD Analog Circuits