C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Verdi, MBIST, DFT micro-architecture, Synopsys Tetramax, EDA Tools, Scan, Mentor Tessent

test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, simulating test vectors, equivalence check DFT DRC rules, ATPG coverage analysis, Cadence Encounter Test, DFTMax, ASIC DFT, timing fixes