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ASIC Design Verification Engineer | UVM | Exp. 8+ years

Cisco DevNet
Bengaluru, India

Skills:

Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Early Applicant

ASIC Design Verification Engineer | UVM | Exp. 8+ years

Cisco Home
Bengaluru, India

Skills:

System Verilog, Building test benches from scratch, ASIC verification using UVM

Early Applicant
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