simvision , Shell, Vcs, Python, Tcl, Verdi, Xcelium, QuestaSim, Uvm, systemverilog

power optimization , Noc, Networking, Cpu, Perl, Verilog, System Verilog, Python, Tcl, LINT, High-Level Synthesis, cdc, power analysis, Peripheral Subsystems, Formal Verification Methodology, Shell-scripting, Synthesis, Timing Closure, RTL Coding, Micro-architecture Development

DDR, Pcie, Ethernet, SRIO, RDMA, verification of ARM RISC-V based sub-systems or SoCs, IP or integration verification of high-speed interfaces, Design Verification, ROCE, RDMA TSO, automated flows and scripts for data exploration analysis and performance verification, 400G Mac, LRO, Congestion Control, waveform debugging tools, PSP, Simulators, SV Assertions, HBM, Formal Emulation, UVM based verification environments, RDMA over converged Ethernet

cache coherency , Soc Architecture, DDR, Shell, Perl, Pcie, Ethernet, Python, Tcl, memory subsystems, Cadence Xcelium, checkers, Uvm, UCIe, coverage-driven verification, Assertions, systemverilog, Synopsys VCS, protocol compliance scoreboards, VIP integration, interrupts, SVA

Regression Testing, Debugging, Functional Coverage, Axi, APB, AMBA Protocols, Uvm, AHB, Assertions, systemverilog, SVA

ASICs, formal verification, GLS low-power DV, LPDDR, Uvm, assertion-based verification, memory system architecture, systemverilog, standard IP components, performance verification

Rtos, Uart, Zephyr, Spi, Embedded Linux, Pcie, I2c, Python, peripheral drivers, lab instrumentation, protocol analyzers, platform firmware development, Oscilloscopes, embedded firmware systems, BootROM, secure boot development

memory controllers , Spi, Pcie, Verilog, I2c, System Verilog, OTN Ethernet based protocols, coverage assertions, VCS simulation flow, Uvm, Axi, VMM, MDIO

Perl, Python, RTL debug skills, SV – UVM Assertions based verification, ARM based system architecture, power aware simulation, RTL design verification, Uvm, systemverilog, Firmware emulation, camera verification, Coverage closure, dpi