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Location : Bangalore
Responsibilities within team:
• Test bench design and implementation.
• Test & coverage plan definition.
• Constrained random test development.
• Coverage specification & analysis.
• Reference model design and implementation.
• Automation of the regression test suite
• Collaboration with architects, logic design, and software engineers ( in remote team setup).
• Architecture review.
• Micro-architecture and code reviews.
• Contribution to the methodology adoption in the team.
• Lab debug simulation support
Desired technical skills :
• Proficiency in Verilog & System Verilog.
• Solid verification skills : planning, problem solving, debug, adversarial testing and random testing.
• Project based work experience with UVM & VMM methodologies.
• Candidate must have experience with architecting the test-plan & test bench.
• Hands on experience with OTN, Ethernet based protocols, PCIe, AXI,I2C,SPI,MDIO & memory controllers etc. will be an added advantage.
• Familiarity with VCS simulation flow, knowledge of coverage & assertions is desirable.
Relevant Experience :
7 to 10 years of hands-on experience in functional verification.
Job ID: 150787035
Skills:
random testing , Oops, Fpga, Pcie, Verilog, System Verilog, coverage assertions, Debug, Ethernet based protocols, VCS simulation flow, Otn, Uvm, VMM, AXI memory controllers, adversarial testing
Skills:
code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage
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