FPGA Design, Static Timing Analysis, Synthesis, Timing Closure, systemverilog, Code coverage analysis, RTL design using Verilog

memory controllers , Uart, Spi, Hdl Languages, Pcie, Verilog, I2c, Unix Systems, Otn, Uvm, Microsemi FPGAs, systemverilog, Ethernet-based protocols, Axi, quartus, VHDL, scripting tools, Vivado, VMM, Libero

FPGA Design, Verilog, systemverilog, Xilinx Vivado, altera quartus, Peripheral Protocols

hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, test benches, Rtl Design, UVM verification flow, Synthesis, Timing Closure, Verification, Debug, Simulation

Fast Fourier Transform, Digital Signal Processing, Verilog, System Verilog, Xilinx FPGA architectures, FPGA development, OFDM, complex algebra, Vivado, Rtl Design, linear algebra, AXI4 Lite, AXI4 Stream, baseband processing

code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage

Tcl Scripting, Verilog, Rtl Design, FPGA hardware platforms, VHDL, FPGA development, Questasim, Timing Analysis

random testing , Oops, Fpga, Pcie, Verilog, System Verilog, coverage assertions, Debug, Ethernet based protocols, VCS simulation flow, Otn, Uvm, VMM, AXI memory controllers, adversarial testing