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Job Description
FPGA Design Engineer Job Description
Responsibilities:
* Design and implement FPGA solutions.
* Participate in architecture definition, implementation, and verification phases.
* Develop detailed design specifications.
* Develop and implement block-level RTL, perform synthesis, and achieve timing closure.
* Collaborate with multi-functional teams including hardware, software, diagnostics, and signal integrity groups.
* Assist in complex subsystem-level lab bring-up, integration, and unit test validation.
Required Skills and Experience
:* Experience with Xilinx, Altera, and Microsemi FPGAs
.* Proficiency in HDL languages: Verilog, VHDL, and SystemVerilog
.* Hands-on experience with FPGA vendor tools such as Vivado, Quartus, and Libero
.* Practical knowledge of Ethernet-based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART, etc
.* Familiarity with simulation flows like UVM and VMM is an added advantage
.* Basic knowledge of Unix systems and scripting tools
.* 5-8 years of relevant FPGA design experience
.Job ID: 149073295
Skills:
Uart, Spi, Pcie, Verilog, I2c, Unix Systems, Otn, Uvm, Microsemi FPGAs, systemverilog, Ethernet-based protocols, quartus, VHDL, scripting tools, Vivado, VMM, AXI memory controllers, Libero
Skills:
FPGA Design, Verilog, systemverilog, Xilinx Vivado, altera quartus, Peripheral Protocols
Skills:
hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, test benches, Rtl Design, UVM verification flow, Synthesis, Timing Closure, Verification, Debug, Simulation
Skills:
Fast Fourier Transform, Digital Signal Processing, Verilog, System Verilog, Xilinx FPGA architectures, FPGA development, OFDM, complex algebra, Vivado, Rtl Design, linear algebra, AXI4 Lite, AXI4 Stream, baseband processing
Skills:
code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage
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