IR EM Analysis, SI PI Analysis, STA and Timing Closure, Cadence, Tcl Python Scripting, Clock Architecture and CTS, Advanced Node Design Methodologies, AI-assisted Design Flows, Floorplanning and Power Planning, Physical Verification, Low Power Design UPF CPF, Physical Design and Signoff, Synopsys

power integrity , Static Timing Analysis (STA), Python Scripting, MCMM analysis, floorplanning, Netlist to signoff GDSII, CTS routing, Cadence Innovus, Physical design signoff, ECO implementation, Timing Closure, Timing constraints setup hold closure, Placement, Full-chip physical design flow

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Tcl, Shell scripting, Python, Fc, Innovous, Tempus, primetime

AI based EDA tools, HBM HMC memory systems, Fusion Compiler, floorplanning, Cadence Innovus, Partitioning strategies, PPA strategy, UPF, Implementation methodologies, TSMC Tech Node, Signoff methodologies, Congestion strategies, QoR assessments, GDS-II, Physical Design, Large SoCs, Synopsys ICC2, Multi-voltage designs

Technical Leadership, Architectural Circuit Co-Optimization, Physical Design, Clock Distribution Circuit Design, Circuit-Level Timing Noise Integrity, Interconnect Physical Design