Matlab, Post layout parasitic extraction, Schematic generation and simulation, Worst case identification, Process technologies tradeoffs, Monte Carlo analysis, Simulation verification, Block level topology selection, IC system partitioning, Physical layout management, AMs, Analog Circuit Design, Signal grounding and routing tradeoffs, Architectural tradeoff analysis, Spectre, Cadence tool set, Simplis

high-speed TX, analog mixed signal design, EDA Tools, transistor capacitor matching, transistor level circuit design, SERDES, Cadence, compensation techniques, Siemens, noise analysis, Synopsys, Pll