routing, Verilog, Floor Planning, VHDL, Placement, Physical Verification, Clock Tree Synthesis, RTL to GDS flows

redhawk , Scripting, Tcl, Perl, routing, Shell, Python, floorplanning, Physical Verification, variability analysis, EDA Tools, EM, Ir, Placement, primetime, Synopsys ICC2, Cadence Innovus, CTS, low-power design, automation skills, Voltus, Si, Timing Closure, ASIC SOC physical design implementation, StarRC

Placement and Optimization, Adaptive power management techniques, Advanced low-power architectures, Signal Integrity Analysis, Leakage optimization and dynamic power reduction, ASIC SoC physical design, Floor planning and Partitioning, Routing and Congestion Analysis, UPF CPF-based low-power implementation flows, Power gating and retention strategies, Low-power verification and signoff methodologies, Power Planning, Timing Closure, Clock gating methodologies, Physical Verification and Signoff