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Showing 4 jobs
Skills:
C, Git, Shell, Perl, Python, Tcl, Xilinx FPGA, Siemens Veloce, Cadence Zebu, Palladium, Uvm, systemverilog, Vivado, SVA
Skills:
Verilog, Sata, Python, Perl, Usb, Uvm, constrained random verification, functional coverage, PCI Express, systemverilog, VMM, DV methodologies
Skills:
C, Debugging, Shell, Verilog, Tcl, System Verilog, Python, Perl, assertions, directed and constrained random methodologies, Uvm, Metric Driven Verification, formal verification methodologies
Skills:
Verilog, Python, Perl, systemverilog, Uvm
