test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, simulating test vectors, equivalence check DFT DRC rules, ATPG coverage analysis, Cadence Encounter Test, DFTMax, ASIC DFT, timing fixes

Tcl, Verilog, Python, Perl, MBIST, Siemens Mentor Tessent, systemverilog, ATPG, Pre-Silicon test planning, DFT methodologies, DFT Compiler, low power concepts, RTL design for DFT, Scan, IJTAG, Synopsys TetraMAX, DFT Integration Verification, Memory Repair