Static timing analysis, Soc, Verilog, quality assurance, AHB, Timing Constraints, LINT, systemverilog, Design Verification, cdc, Logic Synthesis, ASIC, physical implementation, AXI Stream, low power design, formal equivalence, APB, Dft, power analysis

FEA tools, Debugging, Control loop theory, PCB CAD tools, power management, Circuit Design, Board level analog and digital circuit design, Data analysis using Excel or JMP, PCB schematic design, Troubleshooting

C, Debugging, Python, CPU architecture, Validation, Assembly Programming

hardware engineering , C, Jtag, Verilog, Scripting Languages, System Verilog, IEEE1500, HDLs, memory dump, MBIST, scan dump, formal verification methodologies, CPU micro-architectures, CPU architectures, power management features, testbench components

Usb, DDR, Perl, Pcie, Ethernet, Debugging, Python, Tcl, Uvm, systemverilog, constrained-random verification, coverage closure, functional coverage assertions, CXL, SVA

PERL, Python, Tcl, Synthesis, Formal Equivalence, DRC, Ir, LVS, EM Signoff

Java, Unix, C, Maven, Oracle Database, Design Patterns, Performance Tuning, PostgreSQL, Faircom, Spring Boot, Shell Scripting, Multithreading, Git, Gradle, Linux, Database Design, Concurrent Programming, System Design, Rest Apis, Spring Framework, c-treeDB, Object-Oriented Design, SQL query optimization

Jira, Spirent, Scrum, Agile, Ixia, shell scripting, Python, Jenkins, Git, Qtest, Scapy, SDKs, SAI, GitHub CI, Linux environments, trex

test equipment , Nvme, SAS, Eclipse, Pcie, Sata, C Programming, Scripting Languages, Embedded Firmware, Oscilloscopes, ARM development tools, logic bus analyzers, Assembly