Arm, formal verification, RTL, Digital Design, Uvm, systemverilog, RISC

Debugging, Scripting, RTL Coding, ECO flows, LINT, formal equivalence, cdc

FEA tools, Debugging, Control loop theory, PCB CAD tools, power management, Circuit Design, Board level analog and digital circuit design, Data analysis using Excel or JMP, PCB schematic design, Troubleshooting

Arm, Python, RTL simulation, Debug, functional coverage closure, RISC-V, regression automation, x86 architecture, Uvm, SVA, systemverilog

PERL, Python, Tcl, Synthesis, Formal Equivalence, DRC, Ir, LVS, EM Signoff

virtualization, Memory Management, Perl, Python, System Verilog, IP Sub System design verification, Functional Coverage, Trackers, Assertion, Checkers, HW-SW debug, Uvm, power management fundamentals, coherency protocols, DV test bench, Scoreboards, Post-Silicon bring-up, Virtual Memory concepts