Tcl Scripting, Perl, Shell scripting, Python, CTS, primetime, Fusion Compiler, floorplanning, Tempus, Cadence Innovus, signoff, Power Planning, Physical Verification, routing optimization, Eco, Timing Closure, Placement, RTL-to-GDSII Physical Design flow, Synopsys ICC2

Perl scripting, Tcl Scripting, Python, Sta, setup hold analysis, floorplanning, CTS routing, Cadence Innovus, physical optimization, LVS, MMMC-based implementation, full-chip Physical Design, ECO implementation, physical and timing ECOs, Dft, RTL synthesis, Timing Closure, DRC, Placement

hardware engineering , Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation