accelerated life testing , Statistical Analysis, Reliability Engineering, IEC Standards Interpretation, Root Cause Analysis, Product Risk Assessment, product certification, AFMEA, ReliaSoft, Reliability Demonstration, Minitab, Weibull plus, Dfmea

Root Cause Corrective Action (RCCA), SAP, Unigraphics, Teamcenter, ANSYS APDL, Dfmea, Tolerance stack-ups, Automated design optimization, Solid modeling and analysis tools

Data Analytics, DFMA, Dfs, System Engineering, Material Selection, Value Engineering, component selection, PLM PDM tools, APQP, a3, FRACAS, DVPR, Dfmea, supplier qualification, Value Analysis, Quality Reliability projects

Diameter, SMSC, Rcs, Nas, Kubernetes, Packet Core nodes, Root Cause Analysis, GTPV2, Messaging IMS, PFCP, Volte, AI Literacy, HTTP 2, machine learning insights, SIP, 4G and 5G Core network troubleshooting, VoNR, MMSC, U, Epc, cloud-native environments, 5GC

Maven, Spring Boot, Containers, Java Development, Spring MVC, Python Scripting, Git, Linux, Spring Framework, Kubernetes, Incident troubleshooting, Code reviews, Provisioning, Production Support, Hardware firmware integration, Operational automation, Microservices development, Cloud-native operational tooling, Spring Development, Infrastructure automation, Root-cause analysis, Distributed-system integrations, Production change management, oci

Real Number Modeling (RNM), Verification Coverage Analysis, Cadence Xcelium, coverage analysis, DAC Verification, Root-Cause Analysis, Mixed-Signal Waveform Analysis, Mixed-Signal Simulation, PLL Verification, ADC Verification, Regression Debugging, Mixed-Signal Interfaces, Cadence ADE Assembler, Analog Mixed-Signal Verification, Mixed-Signal Testbench Development, Cadence Mixed-Signal Design Environment, Analog Behavioral Modeling, Mixed-Signal Behavioral Models, Simulation Debugging, Analog Building Blocks, AMS Verification, Verilog-AMS, Cadence Virtuoso, AMS Verification Methodology