Perl, Shell scripting, Python, vManager, Xcelium, Cadence environments, JasperGold, UVM methodologies

UNIX, Verilog, Debugging, design quality checks, SoC connectivity concepts, Simulation, RTL integration, Digital Design, Windows environments, systemverilog, RTL Coding, Ms Office Tools, ASIC SoC design methodologies

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

receivers , Pcie, analog circuits simulation, mixed-signal analog integrated circuit design, PLLs, jitter compliance simulations, SERDES, clock drivers, ADCs, differential buffers, FLLs

Firmware Development, FPGA Design, Verilog, Static Timing, ASIC design flow, Synthesis, datapath timing analysis, digital design principles, high-speed data transmission, systemverilog, CMOS digital circuits, Rtl Design, Dft, front-end tools, mixed signal concepts, Verification, clock design

Shell, Tcl, Verilog, Python, Perl, Modelsim, Uvm, LINT, Questa Formal, systemverilog, JasperGold Formal, Cadence VCS, VHDL, Makefiles, QuestaSim, Cadence Xcelium

control logic , Verilog, Rtl Design, Synthesis, systemverilog, Error handling, cdc, Sta, Ethernet standards, Digital micro-architecture, PCS functionality, Link monitoring, state machines, Packet processing, RDC, Safety mechanisms

Debugging, Scripting, RTL Coding, ECO flows, LINT, formal equivalence, cdc