Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog

code coverage , Design Verification Engineer, Low Power Verification Engineer, Power-Aware Verification Engineer, ASIC Design Verification Engineer, systemverilog, Uvm, Constrained Random Verification, Gate-Level Simulation, Timing Simulation, PAGLS, Testbench Development, VIP Integration, Coverage Closure

code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage

clocking , Ovm, DDR, Pcie, Verilog, Ethernet, Platform bring up in Emulators or Silicon, SOC boot flow, Constrained-random verification environments, Uvm, systemverilog, Power management flows, C SV tests, Low Power Verification, Coverage report generation, System Verilog Assertions, RTL GLS level simulations

Design-for-Debug (DFD) and Verification Debug, Verilog, Usb, Pcie, UVM-based Verification Environment Development, Verification Planning Execution, SoC Subsystem Verification, Testbench Development, Interconnect Verification, systemverilog, Functional Coverage, UFS, Axi, Assertions SVA, EMAC Ethernet, Coverage-driven Verification, AHB, AMBA ATB Protocols

Testplan, Perl, Verilog, Shell scripting, Python, System Verilog, testbench, Pre-silicon verification, Coverage Assertion writing, Uvm

Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage

Perl, Verilog, Python, Cadence Incisive, Xcelium, complex testbenches, Uvm, systemverilog, Synopsys VCS, RTL design concepts, VHDL, formal verification, verification environments, Modelsim