Verilog, Tcl, Python, Perl, Git, MBIST, analog test solutions, DFT architectures, systemverilog, ATPG, LBIST

Vcs, Integration, System Verilog, Synopsys VIPs, processor based SoC level verification, ASIC Design, AXI-AMBA protocol, Verification, Uvm, Validation, waveform analyzer

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, Cadence Virtuoso, 3DIC implementation methodologies, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Soc Architecture, System Verilog, scoreboarding, digital design fundamentals, verification concepts, simulation logs, Uvm, ASIC SoC functional verification, waveform tools, constrained-random stimulus, BUS Protocols, assertions, functional coverage, SVA

Usb, Uart, Spi, Gpio, DDR, Shell, Perl, I2c, Python, Tcl, Cadence Incisive, PCIe Gen3, Uvm, Verification IP, UPF, systemverilog, Synopsys VCS, Axi, MIPI, APB, AHB

Perl, Python, Tcl, CDC Lint, low power design, digital circuit design principles, RDC, Timing Analysis Concepts, RTL design synthesis, UPF