Clock Tree Synthesis (CTS), Sta, power analysis, PnR Implementation, Leakage Power, Signal Integrity, Dfm, Design Closure, Physical Design, Placement, Floor Planning, Low Power Verification, Timing Signoff

Scripting, EMIR Signoff flow, Data Analysis, In-rush current profiles, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, On-die power gating, Problem Solving

Logic Design, floorplanning, Physical design flows, Physical design architecture, P R Timing and Physical verification tools, Physical implementation flows

flows and methodologies, Asic Physical Design, collaboration and teamwork, EDA vendor relationships

Sta, PG creation and push-down methodologies, Physical Verification, SoC RTL to GDSII implementation, Scripting flow deployment, RDL knowledge, SoC Full-chip floorplanning, Die file generation, Feed-through planning, Hierarchical design implementation, PnR implementation

power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, LVS, Voltus, MMMC, Timing Closure, DRC, EM IR analysis, full-chip implementation

Scripting, EMIR Signoff flow, Data Analysis, EDA Tools, Dynamic vectored and vectorless Static IR, Power Distribution Network Design, Power grid planning

Logic Design, Physical design architecture, P R Timing and Physical verification tools, floorplanning, Physical implementation flows, Physical design flows

caliber , Clp, Python, Tcl, Synopsys Fusion Compiler, Sta, Synthesis, Signoff, primetime, multi-Vt, physical design implementation, ICC2, low power flows, RTL-to-GDSII flows, Cadence Innovus, Tempus, UPF, PNR, Ansys RedHawk, ICV, multi-voltage