Pcie, Perl, Vcs, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog

Vcs, Integration, System Verilog, Synopsys VIPs, processor based SoC level verification, ASIC Design, AXI-AMBA protocol, Verification, Uvm, Validation, waveform analyzer

Python, System Verilog, Systemc, Pcie, Hybrid test benches, MDV, DV signoffs, SV, CDV, Uvm, Simulation Scripts, test vectors, Coverage, Regression, UCIe, Axi, testplan creation, DV Infrastructure, building testbenches, stimulus based verification, SystemC based reference model