C, C++, Vcs, Soc Architecture, Shell, Perl, Arm, System Verilog, Python, Verdi, AHB protocol, Uvm, Axi, Questa

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Incisive, IMC, analog mixed signal design, Uvm, advanced verification methodologies, xCelium, vManager, Cadence Virtuoso

Pcie, Perl, Vcs, Ethernet, Python, Tcl, Verdi, Uvm, systemverilog

System Verilog, testbench stimulus agent monitor checker development, C based system modelling, Emulation, Uvm, Power aware simulation, tensilica, gate level simulation, formal verification, sub-system verification, C based reference model, failure debugging with Verdi log file, assertion development

Modeling, automation techniques, reusable intellectual property, circuit design verification, silicon correlation, analog and mixed-signal IC design, semiconductor device physics, CMOS technologies, AI-driven engineering tools, product qualification, DRAM, advanced process nodes

Vcs, UVM SoC environment, End-to-end datapath verification methodologies, Xcelium, Questa, Waveform analysis tools, DFT simulation and validation, systemverilog, Clock reset verification

clocking , Ovm, DDR, Pcie, Verilog, Ethernet, Platform bring up in Emulators or Silicon, SOC boot flow, Constrained-random verification environments, Uvm, systemverilog, Power management flows, C SV tests, HSIO, Low Power Verification, Coverage report generation, System Verilog Assertions, RTL GLS level simulations

C, Fpga, DDR, Pcie, Verilog, Scripting, Automation Scripting, C++, Assembly Programming, RTL testbench debug, CHI, Arm-based SoC architecture, memory hierarchy, Uvm, UPF, coverage closure, AI-assisted verification, Ace, Security IP, Emulation, interconnects, post-silicon validation, modern verification methodologies, gate-level simulation, systemverilog, AMBA, coherency, AI-driven tools, formal verification

C, Tcl, Python, Pcie, Perl, Universal Verification Methodology, USB2, HSIO PHY Controllers, systemverilog, UFS, MIPI, Open Verification Methodology, USB3, Skill