Tcl, Verilog, Python, Perl, MBIST, Siemens Mentor Tessent, systemverilog, ATPG, Pre-Silicon test planning, DFT methodologies, DFT Compiler, low power concepts, RTL design for DFT, Scan, IJTAG, Synopsys TetraMAX, DFT Integration Verification, Memory Repair

C, Vcs, Tcl, Verilog, Jtag, Python, Perl, Synopsys Tetramax, MBIST, EDA Tools, Mentor Tessent, Verdi, DFT micro-architecture, Scan

ATPG (Automatic Test Pattern Generation), logic bist , test coverage , Memory BIST (MBIST), DFT architecture, Digital DFT, Scan compression, SoC MCU architecture, DFT protocols, Debug effort

Python, Clp, Tcl, Perl, JTAG BSCAN, MBIST, LEC, SoC DFT Architecture, Logic and DRC analysis, P1500 implementation, ZERO delay and SDF based scan, ATPG DRC analysis, Memory BIST implementation, Hybrid-TK Compression, LPCT, Stuck at TDF, Scan Insertion, power analysis methodologies, Test coverage debug, JTAG simulations, Bridging Cell-aware iddq fault models, LBIST, iJTAG