Vcs, Tcl Scripting, Python, Sta, Synthesis, cdc, SoC integration, Xcelium, QuestaSim, RTL lint, clock reset architecture, systemverilog, quartus, RDC, Vivado, Timing Closure, memory mapping, AMBA AXI AHB APB protocols, ip development

C, C++, Qos, ACL, Python, Policers, L2 and L3 Ethernet switching and routing protocols, TCAM, Embedded system software development

FineSim, Synopsys VCS, SerDes verification, analog mixed signal verification, Xcelium, Verilog-AMS, high-speed design, SystemVerilog-RNM, Cadence Virtuoso, Uvm, Spectre

Design-for-Test (DFT), Verilog, System Verilog, Rtl Design, Physical design considerations, Timing Closure, SoC development, Microarchitecture development, Low-power design methodologies, Architecture Design

Power Integrity (PI), Signal Integrity (SI), Electromagnetic Compatibility (EMC), Power Loss Protection (PLP), I2c, Python, PCB back-end process, Logic Analyzers, AI tools, LPDDR4 5, Buck and Boost PMIC, PCIe interface Gen5 Gen6, Oscilloscopes, SMBus, DC-DC converters, ONFI interface, Load Switch devices, Power Analyzers, LDO, NAND memories, I3C, PCIe analyzers

Feature Validation Test (FVT), Garbage Collection, Nvme, Test Strategies, Debugging, Pcie, Automation Frameworks, Python, Automated reporting systems, Wear levelling, Qualification methodologies, CI/CD-integrated validation solutions, Firmware verification methodologies, AI-centric storage workloads, Bad block management, Validation plans, Error injections

openmpi , ATS, C, C++, Cuda, Memory Management, Pcie, Linux Internals, RDMA, MPI, DMA engines, Libfabric, UCX, ROCm, GPU memory models, P2P, GPUDirect Storage, SHMEM, Gds, GPUDirect RDMA, GDR, IOMMU