Multi-mode multi-corner (MMMC) timing closure, Physical Design, Coherent interconnects, Cache-coherent clusters, RTL-to-GDSII implementation, NoC architectures, Hierarchical design techniques, Timing budgeting, Automated design flows

Perl, Python, Tcl, Innovus, primetime, Calibre, StarRC, ICC2, Voltus

static timing analysis, Perl, Tcl, Synthesis, Makefile scripting, physical design CAD flow, Mentor Calibre, Power Distribution, hierarchical P&R, Cadence Innovus, Cadence Genus, Floor Planning, physical design verification

hardware engineering , Static Timing Analysis (STA), Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation

C, Perl, Tcl, C++, Routing, Clock Planning, Physical Verification, floorplanning, Timing Closure, Physical Design Implementation, Innovus, Calibre, primetime, Placement, ICC2, LEC, EDA Tools

Tcl, Cursor, Python, RTL-to-GDSII flow, AI concepts, Claude, layout closure, timing convergence, Cadence Innovus, Place And Route, AI technologies, design implementation, Physical Design, Synopsys ICC2, Codex, Synthesis, standard place-and-route flows, tool-specific scripting, Clock Tree Synthesis

Tcl, Python, Logical Equivalence, Synthesis, Timing Analysis, Physical Verification DRC LVS ERC, Physical design flows, Place And Route, EDA Tools, Budgeting, floorplanning, Clock CTS

power integrity , Routing, Synthesis, Multi-Voltage Domains, Sign-off, Physical Design implementation, Placement, Low-Power Design, Physical Verification, Timing Closure, floorplanning, CTS